顔写真 准教授 
周 金佳 
シュウ キンカ 
ZHOU Jinjia 



日本学術振興会  特別研究員(DC)  2011/04-2013/03 
日本学術振興会  特別研究員(PD)  2013/04-2013/07 
早稲田大学  次席研究員  2013/07-2016/08 
法政大学  理工学研究科  准教授  2016/09-現在 

上海交通大学  電子電気工学  学部  2007/07 
早稲田大学大学院  情報生産システム研究  修士課程  2010/09 
早稲田大学大学院  情報生産システム研究  博士課程  2013/03 

博士(工学)  早稲田大学 

Algorithms and ASIC/FPGA architectures for multimedia signal processing 


遠隔医療システム向け映像圧縮技術の開発  科学研究費  科学技術振興機構(JST)  戦略的創造研究推進事業(さきがけ)研究発展・新型コロナ対策  2020/04/01-2021/06/30 
超高スループット動画像エンコーダーの最適化設計の研究  日本学術振興会  特別研究員奨励費  2011/04-2013/03 

A Configurable Fixed-Complexity IME-FME Cost Ratio Based Inter Mode Filtering Method in HEVC Encoding  LI Muchen, ZHOU Jinjia, GOTO Satoshi  IIEEJ transactions on image electronics and visual computing  The Institute of Image Electronics Engineers of Japan  8/ 1, 58-70  2020  2188-191X  URL 
A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor  ZHANG Shuping, ZHOU Jinjia, ZHOU Dajiang, KIMURA Shinji, GOTO Satoshi  IEICE Transactions on Electronics  一般社団法人 電子情報通信学会  100/ 3, 223-231  2017  0916-8524  URL  <p>In this paper, a hamburger architecture with a 3D stacked reconfigurable memory is proposed for a 4K motion estimation (ME) processor. By positioning the memory dies on both the top and bottom sides of the processor die, the proposed hamburger architecture can reduce the usage of the signal through-silicon via (TSV), and balance the power delivery network and the clock tree of the entire system. It results in 1/3 reduction of the usage of signal TSVs. Moreover, a stacked reconfigurable memory architecture is proposed to reduce the fabrication complexity and further reduce the number of signal TSVs by more than 1/2. The reduction of signal TSVs in the entire design is 71.24%. Finally, we address unique issues that occur in electronic design automation (EDA) tools during 3D large-scale integration (LSI) designs. As a result, a 4K ME processor with 7-die stacking 3D system-on-chip design is implemented. The proposed design can support real time 3840 × 2160 @ 120 fps encoding at 130 MHz with less than 540 mW.</p> 
研究論文(国際会議プロシーディングス)  14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications.  Dajiang Zhou,Shihao Wang,Heming Sun,Jian-Bin Zhou,Jiayi Zhu,Yijin Zhao,Jinjia Zhou,Shuping Zhang,Shinji Kimura,Takeshi Yoshimura,Satoshi Goto  2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016  IEEE  266-268  2016  10.1109/ISSCC.2016.7418009 
研究論文(学術雑誌)  Low-Power Motion Estimation Processor with 3D Stacked Memory.  Shuping Zhang,Jinjia Zhou,Dajiang Zhou,Shinji Kimura,Satoshi Goto  IEICE Transactions  98-A/ 7, 1431-1441  2015  URL 
研究論文(学術雑誌)  Ultra-High-Throughput VLSI Architecture of H.265/HEVC CABAC Encoder for UHDTV Applications.  Dajiang Zhou,Jinjia Zhou,Wei Fei,Satoshi Goto  IEEE Trans. Circuits Syst. Video Techn.  25/ 3, 497-507  2015  10.1109/TCSVT.2014.2337572 

特許  動き推定装置及び動き推定プログラム  特願2013-018967  2013/02/01  特開2014-150467  2014/08/21 
特許  動き推定装置及び動き推定プログラム  特願2013-018967  2013/02/01  特開2014-150467  2014/08/21  特許第5726220号  2015/04/10 

ISSCC 2016 Takuo Sugano Award for Outstanding Far-East Paper  2016 
STARC Symposium Best Presentation Award  2013 
Chinese Goverment Award  2013 
STARCシンポジウム優秀賞  2013 
中国政府優秀留学生賞  2013